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Silicon Labs /BGM240PB32VNN /GPIO_S /USART0_ROUTEEN

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Interpret as USART0_ROUTEEN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CSPEN)CSPEN 0 (RTSPEN)RTSPEN 0 (RXPEN)RXPEN 0 (CLKPEN)CLKPEN 0 (TXPEN)TXPEN

Description

USART0 pin enable

Fields

CSPEN

CS pin enable control bit
RTSPEN

RTS pin enable control bit
RXPEN

RX pin enable control bit
CLKPEN

SCLK pin enable control bit
TXPEN

TX pin enable control bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data